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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840022
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
FEATURES
* 1 LVCMOS/LVTTL output, 7 output impedence * Crystal oscillator interface designed for 25MHz, 18pF parallel resonant crystal * Output frequencies: 125MHz or 62.5MHz (selectable) * RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.55ps (typical) * RMS phase noise at 125MHz: Offset Noise Power 100Hz .............. -106.3 dBc/Hz 1KHz .............. -126.3 dBc/Hz 10KHz .............. -131.7 dBc/Hz 100KHz .............. -130.8 dBc/Hz * 3.3V operating supply * 0C to 70C ambient operating temperature * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS840022 is a Gigabit Ethernet Clock Generator and a member of the HiPerClocksTM HiPerClockSTM family of high performance devices from ICS. The ICS840022 uses a 25MHz crystal to synthesize 125MHz or 62.5MHz. The ICS840022 has excellent phase jitter performance, over the 1.875MHz - 20MHz integration range. The ICS840022 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space.
ICS
FUNCTION TABLE
Inputs FREQ_SEL 0 1 Output Frequencies (with a 25MHz crystal) 125MHz 62.5MHz
BLOCK DIAGRAM
OE FREQ_SEL
PIN ASSIGNMENT
VDDA OE XTAL_OUT XTAL_IN 1 2 3 4 8 7 6 5 VDD Q0 GND FREQ_SEL
XTAL_IN
OSC
XTAL_OUT
Phase Detector
VCO
560MHz-680MHz w/25MHz Ref.
/5
0
Q0
ICS840022
8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View
/10
1
M = /25 (fixed)
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 840022AG www.icst.com/products/hiperclocks.html REV. A JANUARY 11, 2005
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840022
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
Type Power Input Input Input Power Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3, 4 5 6 7 8 Name VDDA OE XTAL_OUT, XTAL_IN FREQ_SEL GND Q0 VDD Analog supply pin. Output enable pin. When HIGH, Q0 output is enabled. Pullup When LOW, forces Q0 to HiZ state. LVCMOS/LVTTL interface levels. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. Power supply ground. Single-ended clock output. LVCMOS/LVTTL interface levels. 7 output impedence. Core supply pin.
Output Power
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance Input Pullup Resistor Input Pulldown Resistor Output Impedance VDD, VDDA = 3.465V Test Conditions Minimum Typical 4 TBD 51 51 15 Maximum Units pF pF K K
TABLE 3. CONROL FUNCTION TABLE
Control Inputs OE 0 1 Output Q0 Hi-Z Active
840022AG
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REV. A JANUARY 11, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840022
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V 101.7C/W (0 mps) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C
Symbol VDD VDDA IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 45 8 Maximum 3.465 3.465 Units V V mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL VOH Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current OE FREQ_SEL OE FREQ_SEL VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -150 -5 2.6 0.5 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 5 150 Units V V A A A A V V
Output High Voltage; NOTE 1
VOL Output Low Voltage; NOTE 1 NOTE 1: Outputs terminated with 50 to VDD/2. See Parameter Measurement Information Section, "3.3V Output Load Test Circuit".
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Test Conditions Minimum Typical Fundamental 25 50 7 MHz pF Maximum Units
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C
Symbol fOUT Parameter Output Frequency 125MHz, (Intergration Range: 1.875MHz - 20MHz) 62.5MHz, (Intergration Range: 1.875MHz - 20MHz) 20% to 80% Test Conditions Minimum Typical 125 62.5 0.55 0.50 350 50 Maximum Units MHz MHz ps ps ps %
REV. A JANUARY 11, 2005
tjit(O)
tR / tF
RMS Phase Jitter ; NOTE 1 Output Rise/Fall Time
odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plot.
840022AG
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840022
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
TYPICAL PHASE NOISE AT 62.5MHZ (3.3V)
-10 -20 -30 -40 -50
Gb Ethernet Filter 62.5MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.55ps (typical)
0
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k
Raw Phase Noise Data
TYPICAL PHASE NOISE AT 125MHZ (3.3V)
0 -20 -30 -40 -50
Phase Noise Result by adding Gb Ethernet Filter to raw data
1M 10M 100M 100k
OFFSET FREQUENCY (HZ)
Gb Ethernet Filter 125MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.50ps (typical)
-10
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110
Raw Phase Noise Data
-120 -130 -140 -150 -170 -180 -190 100 1k
Phase Noise Result by adding Gb Ethernet Filter to raw data
10k 100k 1M 10M 100M
-160
OFFSET FREQUENCY (HZ)
840022AG
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REV. A JANUARY 11, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840022
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V 5%
Phase Noise Plot
Noise Power
V DD
Qx
SCOPE
LVCMOS
GND
Phase Noise Mask
f1
Offset Frequency
f2
-1.65V 5%
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
V
DD
Q0
Pulse Width t
2
80% 20% tR
80% 20% tF
PERIOD
Clock Outputs
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
840022AG
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REV. A JANUARY 11, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840022
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS840022 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin.
3.3V VDD .01F 10
V DDA .01F 10F
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS840022 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 22p
Figure 2. CRYSTAL INPUt INTERFACE
840022AG
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REV. A JANUARY 11, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840022
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
output frequency. The C1 = 22pF and C2pF = 33pF are recommended for frequency accuracy. For different board layout, the C1 and C2 values may be slightly adjusted for optimizing frequency accuracy.
APPLICATION SCHEMATIC
Figure 3A shows a schematic example of the ICS840022. An example of LVCMOS termination is shown in this schematic. Additional LVCMOS termination approaches are shown in the LVCMOS Termination Application Note. In this example, an 18pF parallel resonant 25MHz crystal is used for generating 125MHz
VDD
R2 10
VDDA
VDD
C3 10uF
C4 0.1u
U1
R1 1K
1 2 3 4
OE
VDDA OE XTAL_OUT XTAL_IN
VDD Q0 GND FREQ_SEL
8 7 6 5
VDD Q
R3 33
Zo = 50 Ohm
FRE_SEL
C2 33pF
X1
ICS840022
C1 22pF
C5 0.1u
LVCMOS
VDD=3.3V
FIGURE 3A. ICS840022 SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 3B shows an example of ICS840022 P.C. board layout. The crystal X1 footprint shown in this example allows installation of either surface mount HC49S or through-hole HC49 package. The footprints of other components in this example are listed
in the Table 7. There should be at least one decoupling capacitor per power pin. The decoupling capacitors should be located as close as possible to the power pins. The layout assumes that the board has clean analog power ground plane.
TABLE 7. FOOTPRINT TABLE
Reference C1, C2 C3 C4, C5 Size 0402 0805 0603
R1, R2, R3 0603 NOTE: Table 7, lists component sizes shown in this layout example.
FIGURE 3B. ICS840022 PC BOARD LAYOUT EXAMPLE
840022AG
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REV. A JANUARY 11, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840022
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 8. JAVS. AIR FLOW TABLE
FOR
8 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2.5
89.8C/W
TRANSISTOR COUNT
The transistor count for ICS840022 is: 1984
840022AG
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REV. A JANUARY 11, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840022
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
8 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 9. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 2.90 6.40 BASIC 4.50 Millimeters Minimum 8 1.20 0.15 1.05 0.30 0.20 3.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
840022AG
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REV. A JANUARY 11, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840022
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
Marking 0022A 0022A Package 8 lead TSSOP 8 lead TSSOP Count tube 2500 tape & reel Temperature 0C to 70C 0C to 70C
TABLE 10. ORDERING INFORMATION
Part/Order Number ICS840022AG ICS840022AGT
The aforementioned trademarks, HiPerClockSTM and FEMTOCLOCKSTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 840022AG
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REV. A JANUARY 11, 2005

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